1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, to a needle alignment verification circuit and method for verifying the alignment between a needle and a pad of a semiconductor device.
2. Description of Related Art
In general, semiconductor devices are manufactured on a semiconductor wafer in die form, separated from each other and packaged. Each of the semiconductor devices undergoes a variety of tests in the semiconductor wafer before being separated from each other. For such tests, needles for applying test voltages and/or signals need to be aligned with respective pads of each semiconductor device.
FIG. 1 is a diagram illustrating a method of verifying the alignment of needles within a semiconductor device. As illustrated in FIG. 1, a semiconductor device 30 includes a sensor pad 33. To test the alignment of needles, the sensor pad 33 is connected to the needle of a probe card 200. A tester 100 provides a probe signal to the sensor pad 33 through the needle of the probe card 20. When the alignment between the sensor pad 33 and the needle is abnormal, a circuit element (not shown) connected to the sensor pad 33 operates and generates a predetermined response signal. Accordingly, a measurer can be aware of the abnormal alignment that occurs while a test is performed.
As illustrated in FIG. 1, in a semiconductor device, a channel of the tester 100 is assigned for verifying the alignment of needles. Due to technological limitations, the number of channels of the tester 100 is limited. The assignment of the channel of the tester 100 to the verifying of the alignment of needles reduces the number of channels available for other uses. As a result, in the semiconductor device, a problem arises in that the overall test time increases due to a shortage of channels.
Therefore, a need exists for a needle alignment verifying circuit and method for verifying the alignment between needles and the pads of the semiconductor device.